Field of the Invention
The present invention provides a semiconductor packaging structure and a manufacturing method for the same. In particular, the present invention provides a semiconductor packaging structure of a chip scale and a manufacturing method for the same.
Descriptions of the Related Art
As miniaturization of electronic products has become more common, semiconductor packaging structures have to be downsized as well. In current semiconductor packaging technologies, a semiconductor packaging structure packaged on a chip scale is preferred to satisfy the demand of downsizing.
Taiwan Patent NO. I251912 discloses a conventional wafer-level chip packaging structure 1 shown in FIG. 1. The conventional wafer-level chip packaging structure 1 generally comprises a wafer 11, a plurality of aluminum pads 12, a dielectric layer 13 and a plurality of redistribution circuit layers 14. The aluminum pads 12 are disposed on the wafer 11, while the dielectric layer 13 is formed on the wafer 11 and the aluminum pads 12. A plurality of openings is formed in the dielectric layer 13 to expose the aluminum pads 12. The redistribution circuit layers 14 are stacked on the dielectric layer 13 and electrically connected with the aluminum pads 12 respectively.
During the manufacturing process of the aforesaid conventional semiconductor packaging structure, usually at least two alignment steps are required: one is used to form the openings in the dielectric layer 13, and the other is used to form the redistribution circuit layers 14. As the number of alignment steps is increased, the overall manufacturing time of the semiconductor packaging structure is prolonged and the manufacturing cost is increased.
Additionally, the redistribution circuit layers 14 of the conventional semiconductor packaging structure are stacked on the dielectric layer 13, so only one surface of the redistribution circuit layers 14 is in contact with the dielectric layer 13. As such, the bonding force between the redistribution circuit layers 14 and the dielectric layer 13 is relatively poor so that the redistribution circuit layers 14 tend to peel off from the dielectric layer 13 during subsequent processes.
Accordingly, a need exists in the art to provide a semiconductor packaging structure which is capable of improving at least one of the aforesaid drawbacks and a manufacturing method for the same.